1. Field of the Invention
The present invention relates to a semiconductor memory which automatically refreshes memory cells.
2. Description of the Related Art
There is a technique for reducing power consumption in a DRAM having a self-refresh mode, by assigning a memory block and a word line to low-order bits and high-order bits of a refresh address generated in the DRAM and lowering the reset frequency of address predecode signals during the self-refresh mode (for example, disclosed in Japanese Unexamined Patent Application Publication No. Hei 9-161477).
Also, in recent years, a semiconductor memory called a pseudo SRAM has been developed. The pseudo SRAM includes DRAM memory cells (dynamic memory cells) and operates as an SRAM by internally, automatically performing a refresh operation to the memory cells. The dynamic memory cell used in the pseudo SRAM is small in area. Therefore, the pseudo SRAM of a large capacity can be developed with a low cost per bit.
In the DRAM, the reception of an access request is disabled during the self-refresh mode. Accordingly, the only access to the memory cells during the self-refresh mode is the refresh operation. Since the refresh address is sequentially incremented or decremented, the address of the memory cell to be accessed (refreshed) next is known. In contrast, in the pseudo SRAM, the access request is received also during a standby period. Hence, the address of the memory cell to be accessed next cannot be known until an external address is received. Accordingly, the technique described in the above document is not applicable to the pseudo SRAM since it is for the semiconductor memories to operate on condition that no access request is generated.